1. Field
Embodiments of the present invention relate to integrated circuits and, in particular, to integrated circuit fabrication processes.
2. Discussion of Related Art
In general, the basic process used in fabricating integrated circuits includes a material deposition stage, a patterning stage, a material removal stage, a doping stage, and a heating stage. The particular stages used depend on the type of devices to be included on the integrated circuit.
In the deposition stage, many thin layers of material (e.g., films), each with particular properties, are deposited on a silicon wafer using known techniques, such as chemical vapor deposition (CVD). Due to variations in wafer processing tools and/or techniques, sometimes the wafer may have variations in its surface topology. When a layer of material is then deposited on the wafer surface, the deposited layer may conform to the surface topology of the wafer. The result tends to be uneven distribution of material.
Thickness variations can be particularly troublesome if fabricated components are to be used as frequency-selective devices commonly found in communication systems such as cellular telephone systems that are intended to resonate at a particular frequency. This is because the weight distribution of material on the wafer determines the resonance frequency. The resonance frequency determines the channel of operation. When the weight distribution cannot be controlled, the resonance frequency cannot be controlled and thus the operating channel cannot be controlled.
Traditional solutions to thickness variations include adding a chemical mechanical planarization/polishing (CMP) stage to the fabrication process. CMP is a process technology used to planarize (i.e., make flat) one or more layers deposited on a wafer. In a typical CMP process the wafer is rotated and is polished (or planarized) using chemical slurry. This solution is adequate in many instances, but has limitations. For example; CMP is not selective enough and may thin an already thin area on the layer of material while attempting to thin a thicker area. Additionally, using CMP to planarize a layer of material adds an extra stage to the fabrication process.
Another solution involves measuring the resonance frequency of the devices and discarding defective components. This post situ or after the fact solution can be quite expensive, however. For example, the components must are already be fabricated before determining whether they are suitable for use in a particular application.
Other solutions include laser correction, which also is a post situ or post fabrication solution. As a result, it can be expensive and time consuming as well.